module axi4_master (
    input         ACLK,
    input         ARESETN,
    // 写地址通道
    output [3:0]  AWID,
    output [31:0] AWADDR,
    output [7:0]  AWLEN,
    output [2:0]  AWSIZE,
    output [1:0]  AWBURST,
    output        AWVALID,
    input         AWREADY,
    // 写数据通道
    output [31:0] WDATA,
    output [3:0]  WSTRB,
    output        WLAST,
    output        WVALID,
    input         WREADY,
    // 写响应通道
    input  [1:0]  BRESP,
    input         BVALID,
    output        BREADY,
    // 用户控制接口
    input         start_write,
    input  [31:0] base_addr,
    input  [7:0]  data_in,
    input  [7:0]  burst_len
);

// 状态机定义
parameter IDLE        = 3'd0;
parameter WRITE_ADDR  = 3'd1;
parameter WRITE_DATA  = 3'd2;
parameter WAIT_RESP   = 3'd3;

reg [2:0]  state;
reg [7:0]  data_counter;
reg [31:0] awaddr_reg;

// 控制信号初始化
assign AWID    = 4'h0;    // ID固定为0
assign AWBURST = 2'b01;   // INCR地址递增模式[5](@ref)
assign AWSIZE  = 3'b010;  // 4字节对齐(32bit数据总线)[5](@ref)

// 主状态机
always @(posedge ACLK or negedge ARESETN) begin
    if (!ARESETN) begin
        state        <= IDLE;
        AWADDR       <= 32'h0;
        AWLEN        <= 8'h0;
        WDATA        <= 32'h0;
        WSTRB        <= 4'h0;
        WLAST        <= 1'b0;
        AWVALID      <= 1'b0;
        WVALID       <= 1'b0;
        BREADY       <= 1'b0;
        data_counter <= 8'h0;
    end else begin
        case(state)
            IDLE: begin
                if (start_write) begin
                    awaddr_reg  <= base_addr;
                    AWADDR      <= base_addr;
                    AWLEN       <= burst_len - 1;  // 突发长度=AWLEN+1[5](@ref)
                    AWVALID     <= 1'b1;
                    state       <= WRITE_ADDR;
                end
            end
            
            WRITE_ADDR: begin
                if (AWREADY) begin
                    AWVALID <= 1'b0;
                    state   <= WRITE_DATA;
                end
            end
            
            WRITE_DATA: begin
                if (WREADY) begin
                    WDATA    <= {24'h0, data_in};  // 8bit数据对齐低字节
                    WSTRB    <= 4'b0001;           // 低字节选通[5](@ref)
                    WVALID   <= 1'b1;
                    data_counter <= data_counter + 1;
                    
                    if (data_counter == burst_len-1) begin
                        WLAST  <= 1'b1;
                        state  <= WAIT_RESP;
                    end
                end
            end
            
            WAIT_RESP: begin
                WVALID <= 1'b0;
                WLAST  <= 1'b0;
                BREADY <= 1'b1;
                
                if (BVALID && BRESP == 2'b00) begin
                    BREADY       <= 1'b0;
                    data_counter <= 8'h0;
                    state        <= IDLE;
                end
            end
        endcase
    end
end

// 地址递增逻辑[5](@ref)
always @(posedge ACLK) begin
    if (state == WRITE_DATA && WREADY) begin
        awaddr_reg <= awaddr_reg + (1 << AWSIZE);  // 按AWSIZE递增地址
    end
end

endmodule